1. Field Of the Invention
The invention is directed to a method and apparatus for determining whether proper interconnections are made between the components of an electronic system.
The invention is more specifically directed to a scan-based interrogating system which is used in conjunction with a scannable system-under-test (SUT) to verify that proper interconnections have been made, at a board level, between integrated circuit (IC) chips mounted on one or more printed circuit boards, and at a frame or system level, between interconnected boards or frames.
2. Cross Reference to Related Copending Applications
The present application is related to copending U.S. patent application Ser. No. 07/670,289 entitled "SCANNABLE SYSTEM WITH ADDRESSABLE SCAN RESET GROUPS", by Robert Edwards et al, which was filed Mar. 15, 1991 [Atty. Docket No. 7954] and copending U.S. patent application Ser. No. 07/672,951 entitled "SCANNABLE SYSTEM WITH ADDRESSABLE CLOCK SUPPRESS ELEMENTS" by Robert Edwards, which was filed Mar. 21, 1991 [Atty. Docket No. 8037]. Said copending applications are assigned to the assignee of the present application and their disclosures are incorporated herein by reference.
3. Cross Reference to Related Patents
The following U.S. patents are assigned to the assignee of the present application and are further incorporated herein by reference: (A) 4,244,019, DATA PROCESSING SYSTEM INCLUDING A PROGRAM-EXECUTING SECONDARY SYSTEM CONTROLLING A PROGRAM-EXECUTING PRIMARY SYSTEM, issued to Anderson et al, Jan. 6, 1981; (B) 4,752,907, INTEGRATED CIRCUIT SCANNING APPARATUS HAVING SCANNING DATA LINES FOR CONNECTING SELECTED DATA LOCATIONS TO AN I/O TERMINAL, issued to Si, et al. Jun. 21, 1988; (C) 4,819,166, MULTI-MODE SCAN APPARATUS, issued to Si et al Apr. 4, 1989; and (D) 4,661,953, ERROR TRACKING APPARATUS IN A DATA PROCESSING SYSTEM, issued to Venkatesh et al, Apr. 28, 1987.
4. Background
Modern electronic systems are often manufactured in modular form as a plurality of electronic modules connected one to the next by an interconnect network.
When large numbers of modules are involved and/or each module has a relatively large number of interface terminals, the interconnect network tends to be relatively complex and is likely to have manufacturing faults. As system size and/or complexity grows, it becomes more and more important to be able to quickly detect and isolate faults within the interconnect network.
A state-of-the-art mainframe computer system is an example of a system having a large and complex interconnect network. Such a system is typically constructed according to a hierarchy of two, three, or more modular levels. The modular levels can be defined in a bottom to top order as: (1) the packaged integrated circuit level, (2) the board level, (3) the frame level and (4) the system level. Each level is characterized by a unique set of interconnect test requirements.
Looking first at the packaged IC level, each integrated circuit (IC) module encapsulates one or more high-density integrated circuit (IC) chips. As many as 100 or more module interface terminals may be provided on each IC packaging module for connecting each of the encapsulated IC chips to points outside their respective modules. Connections to external parts of the module terminals are typically made with solder and/or pin sockets. These connections are prone to develop faults such as short-circuits, opens or excessive series resistance.
Looking next at the board level, each board can have as many as 100 or more IC packaging modules mounted to it. Other components such as line-terminating resistors and filtering capacitors are also often found on each board. The boards are usually multi-layered and the on-board interconnect network typically comprises thousands of printed circuit traces plus a number of discrete wires and/or multi-wire cables which are used for interconnecting on-board components. As many as 500 to 1,000 or more board interface terminals may be provided on the edge of each board for connecting to off-board points. On-board parts of the interconnect network are prone to develop faults such as short-circuits, opens, incorrect wire-routing, excessive series resistance or excessive line capacitance and/or excessive inductance. (Voltage-based signalling systems are primarily sensitive to excessive capacitance while current-based signalling systems are primarily sensitive to excessive inductance.) Also the interconnect network at this level is susceptible to noise problems such as cross-talk between closely-spaced parallel-running lines.
At the frame level, each frame of the computer system may support as many as 10 to 100, or even more boards. Connections between boards are usually made by way of multi-wire cables or motherboard connectors and buses. Cable and/or motherboard connectors mate with the board interface terminals of each board. Inter-board connections can also be made with discrete, hand-routed wires. The inter-board interconnect structure is prone to the same types of faults as the on-board interconnect structure.
At the system level, the computer system itself may be composed of a plurality of frames or boxes. Inter-frame connections are typically made with relatively long plug-in cables. The most common problems with such cables are simple opens, shorts, and incorrectly routed (e.g., swapped) cables, but these are difficult to locate because of the large numbers of wires involved.
From the above, it is seen that the overall interconnect structure of a mainframe computer system includes many different kinds of electrically conductive linkages and that some of these linkages are numbered in the thousands if not millions. Each linkage presents itself in either an accessible form where it may be probed by direct contact or in a non-accessible form. Examples of non-accessible linkages include fine wires contained inside shielded multi-wire cables, traces buried inside multilayer printed circuit boards, and solder connections made to the bottom of a surface-mounted IC chip package. Signals have to flow successfully and correctly through all the different kinds of interconnect linkages (accessible or non-accessible) to enable proper operation of the computer system. All linkages have to be tested to assure system operability, regardless of whether they are directly accessible or not.
Testing the interconnect structure of a mainframe computer system is a problem because of its size, complexity and the inaccessibility of many of its linkages. The interconnect structure can appear to be a monstrously complex and unmanageable maze of inaccessible linkages, even when viewed only at the board level. The problem becomes compounded at the frame and system levels.
Irrespective of size and complexity, it is necessary to verify that each interface terminal of each module (at the board, frame and system levels) is appropriately connected to other parts of the system and/or isolated from yet other parts of the system in accordance with the system design. Preferably, an automated test means is provided to enable technicians to quickly detect, locate and correct all unintended shorts, opens or miswirings at each of the board, frame and system levels.
The testing of an interconnect structure to detect and/or isolate faults is referred to here as network verification.
As already mentioned, one problem in network verification is that it is often difficult, if not impossible, to make direct contact with the ends of each linkage in a complex interconnect structure. To overcome this problem, the JTAG industry standards group (Joint Test Action Group) has proposed a so-called "boundary scan" architecture for each module and techniques for performing contactless network verification and other types of testing functions using this architecture. A modified version of this has been endorsed by the Institute of Electrical and Electronic Engineers as IEEE standard 1149.1.
Under the JTAG approach, and more currently under the IEEE 1149.1 approach, when a multi-module system is constructed, a module-partitioning ring is distributed around the periphery of each module. Each ring is composed of a relatively large number (e.g., 100 or more) of electronic switches (multiplexers) and scan latches. These components are interposed between the interconnect terminals of their respective module and internal circuits of the module so that, in a test mode, the module-partitioning ring of each module can decouple that module's interconnect terminals from their associated internal circuits. The switches and scan latches of each module-partitioning ring are arranged such that they can selectively drive each decoupled terminal toward a desired voltage level during the test mode and/or such that they can detect a voltage level present at each terminal and relay the detected level to a network analyzing unit.
Numerous publications are available describing details of the JTAG boundary scan technique and variations thereof such as the IEEE 1149.1 standard. By way of example, U.S. Pat. No. 4,875,003 issued Oct. 17, 1989 to Burke, "NON-CONTACT I/O SIGNAL PAD SCAN TESTING OF VLSI CIRCUITS", discloses a use of the boundary scan method for testing the I/O cells of an IC chip. U.S. Pat. No. 4,879,717 issued Nov. 7, 1989 to Sauerwald et al., "TESTABLE CARRIERS FOR INTEGRATED CIRCUITS" discloses a method for testing interconnections between IC circuits mounted on a multi-chip carrier. U.S. Pat. No. 4,980,889 issued Dec. 25, 1990 to DeGuise et al., "MULTI-MODE TESTING SYSTEMS" discloses a CMOS based selector circuit which may be used for boundary scan testing. Two papers respectively entitled "Boundary Scan: A Framework for Structured Design-for-Testing", by Maunder and Beenker; and "Testing a Board with Boundary Scan", by van de Lagemaat and Bleeker also describe the JTAG boundary scan technique, these papers being presented in Proceedings of the 1987 International Test Conference, September 1987, pp. 714-723 and pp. 724-729, respectively.
In brief, network verification in accordance with the JTAG technique comprises the ordered steps of:
(1) Selecting a first interconnect wire (or "net") within a system under test (SUT).
(2) Tracing through the selected net to identify one or more observation points (module interface terminals) which belong to the net and, at the same time, to distinguish them from other observation points of the system (SUT) which do not belong to the selected net.
(3) Tracing through the selected net to identify a net driving point.
(4) Applying a preselected voltage level to the net driving point.
(5) Waiting a sufficient length of time for the applied voltage level to propagate out across the system and settle.
(6) Scanning all observation points of the system to detect what voltage level is present at each of the observation points.
(7) Storing data representing the detected levels in a plurality of distinct memory cells such that there is one data item stored in each memory cell and such that each memory cell corresponds to one of the system observation points.
(8) Comparing the voltage level data stored at step (7) against a list containing the levels expected for each and every observation point of the SUT to thereby determine if the applied voltage level of step (4) has propagated to all expected observation points but not to other observation points.
(9) Flagging out discrepancies between the stored data and the list of expected levels.
(10) Selecting a new driving point and/or a new net and repeating steps (2)-(9).
(11) Repeating step (10) until all nets of the interconnect network have been exhausted.
In one variation of the above JTAG method, the system under test is always initialized at step (1) or (2) so that all or most drive points which can be so latched, are latched to a first voltage level representing logic zero ("0"). A second voltage level representing a logic one ("1") is applied at step (4) to the drive point of the net-under-test. At the comparing step (8), a search is made through all the memory cells of step (7) to find those cells having data items representing the logic one ("1") level. Each and only each of the observation points belonging to the net-under-test should be at logic one ("1").
In cases where on contention, the signal level representing logic one ("1") is dominant over the signal level representing logic zero ("0"), the lack of a logic one ("1") at a singular observation point which is supposed to belong to the net-under-test indicates an open circuit. The presence of a logic zero ("0") at all the observation points of the net-under-test or the presence of a logic one ("1") at unexpected observation points indicates a short, a nonfunctioning line driver, or some other fault.
The above variation of the JTAG test is sometimes referred to as a "walking ones" test because of the migrating pattern of logic ones it generates across the system as the test proceeds. A second variation of the JTAG test is a complimentary "walking zeroes" test which is performed separately and used to check the ability of each net to be individually driven to a second voltage level representing logic zero ("0").
Several problems can be associated with the JTAG network verification method. A number of these are described below as items (a) through (f).
(a) One problem is that large amounts of test data may have to be disadvantageously stored at step (7) and individually addressed for analysis at step (8). A typical system under test (SUT) can have thousands or even millions of observation points. According to step (6), the voltage levels of all these numerous observation points are stored and analyzed in each pass through steps (1)-(8). This is done blindly even though many of the observation points are not associated in any way with the net-under-test. Time and memory space are wasted processing irrelevant data.
(b) A second problem is that the walking ones and zeroes tests are performed separately. The same drive and observation points are addressed twice. This disadvantageously consumes test time.
(c) A third problem is that test management is complicated by having to keep track of which node is supposed to be at logic one or logic zero. This is particularly a problem in systems which have complimentary inverted and noninverted signals in adjacent lines.
(d) A further problem of the JTAG approach is that it only tests for steady-state (D.C.) conditions. It does not concern itself with dynamic attributes of the interconnect network such as the signal propagation times of its linkages or the noise sensitivity of the network.
High-speed digital circuits, such as found in state-of-the-art mainframe computers, typically include line-terminators or other line-conditioning components. These line-conditioning components need to be correctly coupled to system nets (lines) for conditioning the nets to carry high frequency signals and/or to minimize noise.
The JTAG network verification method is not structured to either detect the presence of various types of line-conditioning components or determine whether such line-conditioning components are appropriately coupled to desired ones of the nets.
(e) A yet further problem of the JTAG approach becomes apparent after a system (SUT) is switched from a net-verification test mode to a normal-function mode. The electronic switches (multiplexers) which are interposed between, and used for decoupling, module interface terminals from interior circuits of the module add undesirable delays to the circuit paths that otherwise carry normal-mode signals between modules.
The delay problem is compounded in systems where one or more signals propagate through a series of boundary-scanned modules. As these signals cross through the module-partitioning rings which surround the modules, they are undesirably delayed by the electronic switches (multiplexers) in each of the multiple partitioning rings.
(f) Yet another problem of the JTAG approach is that its module-partitioning rings tend to consume relatively large amounts of circuit area and/or power. In a LSSD (Level Sensitive Scan Design) implementation of the JTAG architecture (or the IEEE 1149.1 architecture), a first clocked scan latch is provided at each terminal that carries a functional signal across the boundary of each module for detecting the voltage level present at that terminal. (As an aside, it is noted that both JTAG and IEEE 1149.1 require latches for sampling all input, output and bidirectional module pins during a nontest functional mode of a testable system.)
A second clocked scan latch plus a multiplexer are provided at each bidirectional or signal outputting terminal (and optionally for signal inputting terminals) of each module for isolating that terminal from its normal-mode drive circuit and for applying a desired voltage level to that terminal during testing. The combination of scan latches and multiplexers disadvantageously consumes circuit space which might be otherwise used to support normal mode functions. The relatively large number of active components in the module-partitioning rings disadvantageously consume power.
A network verification method and apparatus which overcomes these and other problems is disclosed below.